1. Field of the Invention
This invention relates in general to clock signal generation in a microprocessor, and more particularly to an apparatus for enabling a fixed core-to-bus clock ratio while selectively disabling on-board clock ratio control signals.
2. Description of the Related Art
Over the past 30 years, innovations in integrated circuit design and fabrication techniques have resulted in a vast proliferation of desktop computer systems. No longer is ownership of a computer restricted to users in the scientific realm. Rather, desktop computers have become so ubiquitous in the marketplace that they are now on the verge of becoming commodity items. As a result of this surge in desktop system ownership, desktop computer designers have been forced to address a very broad spectrum of consumers, from those desiring high-end performance whose funds are relatively unrestricted to those who choose, primarily because of budget restrictions, to purchase low-end performance systems.
Although technology advances exist that would allow most elements in a desktop computer system to achieve significant performance gains, in order to maintain affordability for the average consumer, desktop computer designers have fundamentally focused on improving the performance of those elements that contribute in great measure to the overall performance of a desktop system. Because a microprocessor is at the heart of the desktop computer system, it follows then that the industry has witnessed microprocessor performance improvements almost an order or magnitude in excess of performance improvements in peripheral system bus devices such as memory, hard disk controllers, and like elements.
As a result, today's microprocessors are capable of operating at speeds roughly five times that of other devices on their system bus. In fact, both microprocessor designers and desktop computer system designers make provisions in their respective products to optimize the use of a fast microprocessor while at the same time minimizing the effects of delays caused by accesses to slower devices on the system bus. One exemplary provision is on-board cache. Present day microprocessors maintain a copy of frequently used data blocks from memory in on-board cache, specifically so that the data blocks can be repeatedly accessed at a faster speed without having to access a slower memory device on the system bus.
Another example of a feature provided by microprocessor designers to maximize the performance of a microprocessor employed in a low-end desktop system is a clock multiplier. Early microprocessors operated at the same speed at remaining devices in a desktop system. In most systems, a bus clock generator provided a bus clock signal to all devices on the system bus, to include the microprocessor. All devices operated at the frequency of the bus clock. However, today's microprocessors have employed the clock multiplier, a logic device internal to the microprocessor, to synchronously generate a core logic clock signal having a frequency up to several times that of the bus clock. The core logic clock is routed to core processing logic in the microprocessor thus enabling it to operate faster than the remaining devices on the system bus.
Early clock multipliers simply doubled the bus clock frequency. More recent microprocessors, however, provide clock ratio control signals that allow a desktop computer designer to choose from a specified range of clock ratios for generation of the core clock signal. Such a feature is useful, particularly in consideration of the fact that production savings can be achieved when a microprocessor having easily configurable features is produced for a wide range of applications. Hence, most desktop computer designers provide a microprocessor on a motherboard that has jumpers to set the state of the clock ratio control signals. By simply installing or removing particular jumpers, the frequency of the core clock can be configured for a number of performance levels.
A more recent affordability feature provided in desktop systems is the ability for an end user to upgrade his system by simply replacing an older microprocessor with an upgraded microprocessor. Typically, rather than solder the older microprocessor directly to the motherboard when the system is produced, a manufacturer will solder a socket to the motherboard from which the microprocessor can be easily removed. The upgraded microprocessor is inserted in its place and, without return to the factory or a service call, the end user has affected a significant performance upgrade on his own.
The ideal upgrade scenario for desktop manufacturers is stated above: replace the older microprocessor with the upgraded microprocessor without a change to jumper settings the motherboard or the requirement to install additional logic devices. Although this ideal is sometimes achieved, such is not always the case. One skilled in the art will appreciate that any of a number of factors can result in departure from the ideal case, such departure being primarily driven by the degree of design information interchange between a microprocessor manufacturer and desktop computer manufacturers. More specifically, a significant problem faced by the industry today regards compatibility of clock ratio control signals provided on older motherboards with what is required to establish a core clock frequency in present day microprocessors.
Older motherboards only provide the capability to configure the state of one clock ratio control signal. But today's microprocessors require that two or three clock ratio signals be configured in order to prescribe a core clock signal frequency. As a result of this incompatibility, owners of desktop computer systems incorporating these older motherboards are precluded from upgrading their systems.
Therefore, what is needed is a microprocessor having a fixed core-to-bus clock ratio, configured during fabrication of the microprocessor, that ignores the states of clock ratio control signals provided by older motherboards.
In addition, what is needed is an apparatus in a microprocessor to permanently disable clock ratio control signals during normal operation, yet having the capability to control the clock ratio during test of the microprocessor.
Furthermore, what is needed is a microprocessor having a selective clock multiplier, whose functionality is configured during fabrication, either to function in accordance with its clock ratio control signals, or to ignore the clock ratio control signals and operate at a fixed clock ratio.